1. Field of the Invention
The present invention relates to a semiconductor wafer and, more specifically, to an improvement of a mark for identifying crystal orientation of a semiconductor wafer provided on the semiconductor wafer for identifying a specific crystal orientation of the semiconductor wafer.
2. Description of the Background Art
An orientation flat serving as a reference for identifying the crystal orientation is provided on a semiconductor wafer. FIG. 6 is a plan view of a semiconductor wafer having the orientation flat. The orientation of a main surface 2 of the semiconductor wafer 1 is (100). One crystal orientation &lt;110&gt; of the semiconductor wafer 1 is in the direction shown by A and in the direction shown by B which is orthogonally intersecting the direction shown by A. An orientation flat 3 is provided on the semiconductor wafer 1 by cutting a portion of an outer periphery of the semiconductor wafer 1 along the direction shown by A. The orientation flat 3 has the following two functions.
First, the orientation flat 3 serves as a reference for alignment in lithography during the manufacturing process of the semiconductor.
Secondly, the orientation flat 3 serves as a reference in dicing the semiconductor wafer into semiconductor chips.
However, provision of the orientation flat on the semiconductor wafer exhibits the following drawbacks. As described above, the orientation flat serves as a reference for alignment. In order to realize precise alignment, the orientation flat must be of some length. Consequently, a large area of the semiconductor wafer is cut away in providing the orientation flat on the semiconductor wafer. Accordingly, the number of semiconductor chips which can be formed on one semiconductor wafer is reduced.
As the orientation flat is provided on the semiconductor wafer, the peripheral portion of the semiconductor wafer comes to be defined by a curve and a line. When the semiconductor wafer having the orientation flat is thermally processed, the outer peripheral portion of the semiconductor wafer does not expand uniformly, thereby causing stress in the semiconductor wafer. Now, when a force is applied to a member having a portion at which the shape of the member is abruptly changed, the stress is concentrated at that portion. As to the semiconductor wafer having the orientation flat, the shape of the semiconductor wafer is abruptly changed at the portion of the orientation flat. Therefore, when the semiconductor wafer is thermally processed, stress is concentrated on the portion having the orientation flat. Consequently, crystal defects are generated at the portion of the orientation flat of the semiconductor wafer. The crystal defects can be seen as slip lines.
FIG. 7 is a plan view of a semiconductor wafer on which slip lines are generated. The orientation of a main surface 5 of a semiconductor wafer 4 is (100). One crystal orientation &lt;110&gt; of the semiconductor wafer 4 is in the direction shown by C and in the direction shown by D which is orthogonal to the direction shown by C. The orientation flat 6 is formed by cutting away a portion of the outer periphery of the semiconductor wafer 4 along the direction of C. Slip lines 7 are generated at the portion of the orientation flat 6 of the semiconductor wafer 4. The slip lines 7 extend in the direction of D. The portion which is discontinued from the curve defining the outer periphery of the semiconductor wafer 4, that is, the portion of the orientation flat 6, must be long to some extent as mentioned above. Therefore, stress is concentrated at a relatively wide range during thermal processing of the semiconductor wafer 4, so that the slip lines 7 are generated in the wide range.
The following two prior art references disclose semiconductor wafers having marks, other than the orientation flat, for identifying the crystal orientation. One is disclosed in Japanese Patent Laying-Open No. 60-119709. In this prior art, a through hole, a semicircular notch or the like is provided on the semiconductor wafer, which is used as a mark for identifying the crystal orientation of the semiconductor wafer.
The specific content will be described in the following. Japanese Patent Laying-Open No. 60-119709 discloses three semiconductor wafers. The first one shown in FIG. 8 has a through hole 9 serving as a mark for identifying the crystal orientation at the center of the semiconductor wafer 8 whose outer periphery is circular. The through hole 9 is an isosceles triangle. A portion at which two sides having the same length intersect with each other is a vertex 10 of the isosceles triangle. A side 11 is facing the vertex 10. A line coupling the side 11 with the vertex 10 seems to identify the crystal orientation of the semiconductor wafer 8.
In the semiconductor wafer 8 shown in FIG. 8, the area of the through hole 9 is made smaller than the area of the wafer which is cut off for providing the orientation flat. Therefore, the consequential loss of the semiconductor wafer 8 can be made smaller than that of the semiconductor wafer having the orientation flat. However, since the distance between the vertex 10 and the side 11 is short, the through hole 9 does not exactly indicate the crystal orientation.
Since the outer periphery of the semiconductor wafer 8 is circular, the outer periphery of the semiconductor wafer 8 expands uniformly when it is thermally processed. Consequently, no stress is generated in the semiconductor wafer 8, and accordingly no slip line is generated in the semiconductor wafer 8.
Another semiconductor wafer disclosed in the Japanese Patent Laying-Open No. 60-119709 is as shown in FIG. 9, which has a through hole and a notch serving as marks for identifying the crystal orientation provided on a semiconductor wafer having circular outer periphery. A circular through hole 13 is provided at the center of the semiconductor wafer 12. A semicircular notch 14 is provided on the outer periphery of the semiconductor wafer 12. A line coupling the through hole 13 and the notch 14 seems to indicate a specific crystal orientation of the semiconductor wafer 12. The loss of the semiconductor wafer 12 is only the areas at both ends of the line, namely, the portion of the through hole 13 and the notch 14. The through hole 13 and the notch 14 may be small, since they are used only for defining a line serving as a reference for identifying crystal orientation. Compared with the orientation flat, the area loss of the semiconductor wafer can be reduced by these marks for identifying the crystal orientation.
As mentioned above, the notch 14 may be small. Therefore, the outer periphery of the semiconductor wafer 12 is approximately circular, so that the outer portions of the semiconductor wafer 12 are expanded approximately uniformly when it is thermally processed. Accordingly, the stress generated in the semiconductor wafer 12 is small, and therefore slip lines are less frequently generated even if the stress is concentrated at the notch 14.
A further semiconductor wafer disclosed in the Japanese Patent Laying-Open No. 60-119709 is as shown in FIG. 10, which has through holes serving as marks for identifying crystal orientation provided on a semiconductor wafer 15 whose outer periphery is circular. Through holes 16 and 17 are provided near the outer periphery of the semiconductor wafer 15, which through holes 16 and 17 are both circular. A line coupling the through holes 16 and 17 seems to identify the crystal orientation of the semiconductor wafer 15. The area loss of the semiconductor wafer 15 can be reduced for the same reason as described above with reference to the semiconductor wafer 12 shown in FIG. 9. Slip lines are not generated in the semiconductor wafer 15 from the same reason as described above with reference to the semiconductor wafer 8 shown in FIG. 8.
Another example of prior art relating to a semiconductor wafer, having a mark other than an orientation flat for identifying the crystal orientation, is disclosed in Japanese Patent Laying-Open No. 63-148614. In the prior art, a mark for identifying the crystal orientation is provided on a semiconductor wafer in the following manner. First, a main surface of a semiconductor wafer having circular outer periphery is irradiated from above by X-ray. The diffracted X-ray is measured by a detector, whereby the crystal orientation of the semiconductor wafer is detected. A mark indicating the crystal orientation is applied on the surface of the semiconductor wafer. Since a mark indicating the crystal orientation is applied on the surface of the semiconductor wafer, there is no area loss of the semiconductor wafer. The outer periphery of the semiconductor wafer is circular, so that the outer periphery of the semiconductor wafer expands uniformly when it is thermally processed. Therefore, no stress is generated in the semiconductor wafer, and accordingly no slip line is generated in the semiconductor wafer.
Semiconductor wafers are manufactured by slicing a bar semiconductor. Since the bar is considerably long, it is difficult to provide a through hole in the longitudinal direction of the bar. Therefore, in the prior art disclosed in the Japanese Patent Laying-Open No. 60-119709 in which a through hole is provided on a semiconductor wafer as a mark for identifying the crystal orientation, the through hole must be provided on the semiconductor wafer after it is sliced. Provision of a through hole in a number of the semiconductor wafer one by one takes much time, reducing efficiency in the producing of semiconductor devices.
As to the prior art examples disclosed in the Japanese Patent Laying-Open No. 60-119709, the mark for identifying the crystal orientation shown in FIG. 8 does not precisely indicate the crystal orientation of the semiconductor wafer, compared with the orientation flat. The following is also a reason of the lower precision in indicating the crystal orientation of this mark for identifying the crystal orientation. Namely, the mark for identifying the crystal orientation shown in FIG. 8 indicates a specific crystal orientation by a line coupling the side 11 and the vertex 10. However, there are two lines coupling the side 11 and the vertex 10. Consequently, the crystal orientation cannot be uniquely indicated by the mark for identifying the crystal orientation. It is the same in the case of the mark for identifying the crystal orientation shown in FIG. 9. Namely, there can be a number of lines coupling the circular through hole 13 and the semicircular notch 14 because of their finite size, so that the crystal orientation cannot be precisely indicated. It is also the same in the case circular marks of finite size, as shown in FIG. 10.
The prior art disclosed in the Japanese Patent Laying-Open No. 63-148614 provides a mark indicating the crystal orientation on the surface of the semiconductor wafer, as described above. Since such a mark cannot not be applied on the bar member before slicing, the mark must be applied on individual semiconductor wafers produced by slicing the bar. Namely, in this prior art also, marks must be applied on the semiconductor wafer one by one, reducing the efficiency in producing semiconductor devices.
In addition, specific disclosure is not given in the Japanese Patent Laying-Open No. 63-148614 about the mark for identifying the crystal orientation applied on the semiconductor wafer. Whether or not the crystal orientation can be precisely indicated by the mark cannot be determined.